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EL5224, EL5324, EL5424
Data Sheet May 11, 2005 FN7004.3
12MHz Rail-to-Rail Buffers + 100mA VCOM Amplifier
The EL5224, EL5324, and EL5424 feature 8, 10, and 12 low power buffers, respectively, and one high power output amplifier. They are designed primarily for buffering column driver reference voltages in TFT-LCD applications as well as generation of the VCOM supply. Each low power buffer features a -3dB bandwidth of 12MHz and features rail-to-rail input/output capability. The high power buffer can drive 100mA and swings to within 2V of each rail. The 8-channel EL5224 is available in 24-pin QFN and 24-pin HTSSOP packages, the 10-channel EL5324 is available in 32-pin QFN and 28-pin HTSSOP packages, and the 12-channel EL5434 is available in the 32-pin QFNQFN package. They are specified for operation over the full -40C to +85C temperature range.
Features
* 8, 10, and 12 channel versions * 12MHz -3dB buffer bandwidth * 150mA VCOM buffer * Operating supply voltage from 4.5V to 16.5V * Low supply current - 6mA total (8-channel version) * Rail-to-rail input/output swing (buffers only) * QFN package - just 0.9mm high * Pb-Free available (RoHS compliant)
Applications
* TFT-LCD column driver buffering and VCOM supply * Electronics notebooks * Computer monitors * Electronics games * Touch-screen displays * Portable instrumentation
Ordering Information
PART NUMBER EL5224IL EL5224IL-T7 EL5224IL-T13 EL5224ILZ (See Note) EL5224ILZ-T7 (See Note) EL5224ILZ-T13 (See Note) EL5224IRE EL5224IRE-T7 EL5224IRE-T13 EL5224IREZ (See Note) EL5224IREZ-T7 (See Note) EL5224IREZ-T13 (See Note) EL5324IL EL5324IL-T7 EL5324IL-T13 EL5324ILZ (See Note) EL5324ILZ-T7 (See Note) PACKAGE 24-Pin QFN 24-Pin QFN 24-Pin QFN 24-Pin QFN (Pb-free) 24-Pin QFN (Pb-free) 24-Pin QFN (Pb-free) 24-Pin HTSSOP 24-Pin HTSSOP 24-Pin HTSSOP 24-Pin HTSSOP (Pb-free) 24-Pin HTSSOP (Pb-free) 24-Pin HTSSOP (Pb-free) 32-Pin QFN 32-Pin QFN 32-Pin QFN 32-Pin QFN (Pb-free) 32-Pin QFN (Pb-free) 7" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" TAPE & REEL PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
Ordering Information (Continued)
PART NUMBER EL5324ILZ-T13 (See Note) EL5324IRE EL5324IRE-T7 EL5324IRE-T13 EL5324IREZ (See Note) EL5324IREZ-T7 (See Note) EL5324IREZ-T13 (See Note) EL5424IL EL5424IL-T7 EL5424IL-T13 EL5424ILZ (See Note) EL5424ILZ-T7 (See Note) EL5424ILZ-T13 (See Note) PACKAGE 32-Pin QFN (Pb-free) 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) 32-Pin QFN 32-Pin QFN 32-Pin QFN 32-Pin QFN (Pb-free) 32-Pin QFN (Pb-free) 32-Pin QFN (Pb-free) 7" 13" 7" 13" TAPE & REEL 13" 7" 13" 7" 13" PKG. DWG. # MDP0046 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5224, EL5324, EL5424 Pinouts
EL5224 (24-PIN HTSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VS+ 5 VIN5 6 VIN6 7 VIN7 8 VIN8 9 VSA+ 10 VINA+ 11 NC 12 THERMAL PAD 24 VOUT1 23 VOUT2 22 VOUT3 21 VOUT4 20 VS19 VOUT5 18 VOUT6 17 VOUT7 16 VOUT8 15 VSA14 VINA13 VOUTA VIN1 1 VIN2 2 VIN3 3 VIN4 4 VIN5 5 VS+ 6 VIN6 7 VIN7 8 VIN8 9 VIN9 10 VIN10 11 VSA+ 12 VINA+ 13 NC 14 THERMAL PAD
EL5324 (28-PIN HTSSOP) TOP VIEW
28 VOUT1 27 VOUT2 26 VOUT3 25 VOUT4 24 VOUT5 23 VS22 VOUT6 21 VOUT7 20 VOUT8 19 VOUT9 18 VOUT10 17 VSA16 VINA15 VOUTA
EL5324 & EL5424 (32-PIN QFN) TOP VIEW
26 VOUT2* 28 VOUT0 27 VOUT1
EL5224 (24-PIN QFN) TOP VIEW
21 VOUT1 20 VOUT2 19 VOUT3 18 VOUT4 17 VSTHERMAL PAD 16 VOUT5 15 VOUT6 14 VOUT7 13 VOUT8 VOUTA 10 VINA+ 9 VINA- 11 VSA+ 8 VSA- 12
32 VIN2*
31 VIN1
30 VIN0
24 VIN2
23 VIN1
29 NC
VIN3 1 VIN4 2 VIN5 3 VS+ 4 VIN6 5 VIN7 6 VIN8 7 VIN9 8 VIN10 9 VIN11* 10 VINA+ 12 VOUTA 13 VINA- 14 VSA- 15 VOUT11* 16 VSA+ 11 THERMAL PAD
25 VOUT3 24 VOUT4 23 VOUT5 22 VS21 VOUT6 20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10
VIN3 1 VIN4 2 VS+ 3 VIN5 4 VIN6 5 VIN7 6 VIN8 7
*Not available in EL5324
2
22 NC
EL5224, EL5324, EL5424
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current (VOUT0-9) . . . . . . . . . . 30mA Maximum Continuous Output Current (VOUTA). . . . . . . . . . . 150mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0, RL = 10k, RF = RG = 20k, CL = 10pF to 0V, Gain of VCOM = -1, and TA = 25C Unless Otherwise Specified CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
INPUT CHARACTERISTICS (REFERENCE BUFFERS) VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 1V VOUT 14V 0.992 VCM = 0V (Note 1) VCM = 0V 2 5 2 1 1.35 1.008 50 14 mV V/C nA G pF V/V
INPUT CHARACTERISTICS (VCOM BUFFER) VOS TCVOS IB RIN CIN VREG Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Load Regulation VCOM = 6V, -100mA < IL < 100mA -20 VCM = 7.5V (Note 1) VCM = 7.5V 1 3 2 1 1.35 +20 100 4 mV V/C nA G pF mV
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = 7.5mA IL = 7.5mA 14.85 120 50 14.95 140 150 mV V mA
OUTPUT CHARACTERISTICS (VCOM BUFFER) VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current 50 to 7.5V 50 to 7.5V 13.5 1 14 160 1.5 V V mA
POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio Reference buffer VS from 5V to 15V VCOM buffer, VS from 5V to 15V IS Total Supply Current EL5224 (no load) EL5324 (no load) EL5424 (no load) DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) SR tS BW Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth -4V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF 7 15 250 12 V/s ns MHz 55 60 5 6 7 80 100 6.8 7.8 8.8 8 9.5 11 dB dB mA mA mA
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EL5224, EL5324, EL5424
Electrical Specifications
PARAMETER GBWP PM CS NOTES: 1. Measured over operating temperature range 2. Slew rate is measured on rising and falling edges VS+ = +15V, VS- = 0, RL = 10k, RF = RG = 20k, CL = 10pF to 0V, Gain of VCOM = -1, and TA = 25C Unless Otherwise Specified (Continued) DESCRIPTION Gain-Bandwidth Product Phase Margin Channel Separation CONDITIONS RL = 10k, CL = 10pF RL = 10k, CL = 10pF f = 5MHz MIN TYP 8 50 75 MAX UNIT MHz dB
Pin Descriptions
24-PIN HTSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 24-PIN QFN 23 24 1 2 3 4 5 6 7 8 9 22 10 11 12 13 14 15 16 17 18 19 20 21 32-PIN QFN 31 32 (Note 1) 1 2 4 3 5 6 7 11 12 29 13 14 15 19 20 21 23 22 24 25 26 (Note 1) 27 8 9 10 (Note 1) 16 (Note 1) 17 18 28 30 NOTE: 1. Not available in EL5324IL 18 19 28-PIN HTSSOP 1 2 3 4 6 5 7 8 9 12 13 14 15 16 17 20 21 22 24 23 25 26 27 28 10 11 PIN NAME VIN1 VIN2 VIN3 VIN4 VS+ VIN5 VIN6 VIN7 VIN8 VSA+ VINA+ NC VOUTA VINAVSAVOUT8 VOUT7 VOUT6 VOUT5 VSVOUT4 VOUT3 VOUT2 VOUT1 VIN9 VIN10 VIN11 VOUT11 VOUT10 VOUT9 VOUT0 VIN0 Input Input Input Input Power Input Input Input Input Power Positive input of VCOM Not connected Output of VCOM Negative input of VCOM Power Output Output Output Output Power Output Output Output Output Input Input Input Output Output Output Output Input PIN FUNCTION
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EL5224, EL5324, EL5424 Typical Performance Curves
20 NORMALIZED MAGNITUDE (dB) 10 0 -10 -20 -30 100K 150 562 VS=7.5V CL=10pF 10k 1k 20 NORMALIZED MAGNITUDE (dB) 10 0 47pF -10 -20 -30 100K 12pF VS=7.5V RL=10k
1000pF 100pF
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL (BUFFER)
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL (BUFFER)
100 PSRR+ 80 PSRR (dB) 60 40 20 0 1K PSRR-
VS=7.5V OUTPUT IMPEDANCE ()
600 480 360 240 120
VS=7.5V TA=25C
10K
100K FREQUENCY (Hz)
1M
10M
0 100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. PSRR vs FREQUENCY (BUFFER)
FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER)
80 VOLTAGE NOISE (nV/Hz) 100 OVERSHOOT (%) 70 60 50 40 30 20 10 1 10K 100K 1M FREQUENCY (Hz) 10M 100M 0 10
VS=7.5V RL=10k VIN=100mV
10
100 CAPACITANCE (pF)
1K
FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY (BUFFER)
FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER)
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EL5224, EL5324, EL5424 Typical Performance Curves (Continued)
10 8 6 STEP SIZE (V) 4 2 0 -2 -4 -6 -8 -10 200 250 300 350 400 450 500 550 600 650 SETTLING TIME (ns) 0.006 1K 10K FREQUENCY (Hz) 100K VS=7.5V RL=10k CL=12pF THD + NOISE (%) 0.018 0.016 0.014 0.012 0.01 0.008 VS=5V RL=10k VIN=2VP-P
FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER)
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (BUFFER)
12 10 8 VOP-P (V) 6 4 2 VS=5V RL=10k 100K 1M 10M NORMALIZED MAGNITUDE (dB)
4 AV=5 2 0 -2 -4 AV=1
0 10K
-6 100
VS=7.5V CL=1F 1K 10K 100K 1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER)
FIGURE 10. FREQUENCY RESPONSE (VCOM)
0mA 5mA RS=0 CL=200pF 0V RS=10 CL=4.7nF RS=10 CL=1nF
5mA/DIV
5mA 0mA RS=10 CL=1nF
5mA/DIV
500mV/DIV
0V RS=0 CL=200pF RS=10 CL=4.7nF
500mV/DIV
M=1s/DIV VS=7.5V VIN=0V
M=1s/DIV VS=7.5V VIN=0V
FIGURE 11. TRANSIENT LOAD REGULATION - SOURCING (BUFFER)
FIGURE 12. TRANSIENT LOAD REGULATION - SINKING (BUFFER)
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EL5224, EL5324, EL5424 Typical Performance Curves (Continued)
M=4s/DIV, VS=7.5V, VIN=0V 0mA -100mA 100mA/DIV 100mA 0mA 100mA/DIV M=4s/DIV, VS=7.5V, VIN=0V
0V CL=1F
20mV/DIV
0V CL=1F
20mV/DIV
FIGURE 13. TRANSIENT LOAD REGULATION - SOURCING (VCOM)
FIGURE 14. TRANSIENT LOAD REGULATION - SINKING (VCOM)
VS=7.5V, RL=10k, CL=12pF VS=7.5V
50mV/DIV
1V/DIV
200ns/DIV
1s/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE (BUFFER)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 POWER DISSIPATION (W) 2.5 2.703W 2 1.5 1 0.5 0 QFN24 JA=37C/W QFN32 JA=35C/W 2.857W
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE (BUFFER)
0.8 POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 758mW 714mW QFN32 JA=132C/W QFN24 JA=140C/W
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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EL5224, EL5324, EL5424 Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.333W 3.030W HTSSOP28 JA=30C/W HTSSOP24 JA=33C/W POWER DISSIPATION (W) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 0.8 833mW 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 50 75 85 100 125 150 0 0 25 50 75 85 100 125 150 HTSSOP24 JA=120C/W 909mW
3.5 POWER DISSIPATION (W) 3 2.5 2 1.5 1 0.5 0
HTSSOP28 JA=110C/W
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Applications Information
Product Description
The EL5224, EL5324, and EL5424 unity gain buffers and 100mA VCOM amplifier are fabricated using a high voltage CMOS process. The buffers exhibit rail-to-rail input and output capability and has low power consumption (600A per buffer). When driving a load of 10k and 12pF, the buffers have a -3dB bandwidth of 12MHz and exhibits 18V/s slew rate. The VCOM amplifier exhibits rail-to-rail input. The output can be driving to within 2V of each supply rail. With a 1F capacitance load, the GBWP is about 1MHz. Correct operation is guaranteed for a supply range of 4.5V to 16.5V.
5V 10s VS=5V TA=25C VIN=10VP-P
5V
FIGURE 21. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
The Use of the Buffers
The output swings of the buffers typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 21 shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P.
SHORT-CIRCUIT CURRENT LIMIT The buffers will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects. OUTPUT PHASE REVERSAL The buffers are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 22 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur.
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OUTPUT
INPUT
EL5224, EL5324, EL5424
VBOOST 1V 10s R1 VDDCOM VSSCOM
R2
IPCOM + INCOM -
VCOM VCOM 1F CERAMIC LOW ESR
1V
VS=2.5V TA=25C VIN=6VP-P
FIGURE 23. VCOM USED AS A VOLTAGE BUFFER
FIGURE 22. OPERATION WITH BEYOND-THE-RAILS INPUT
UNUSED BUFFERS It is recommended that any unused buffers have their inputs tied to the ground plane. DRIVING CAPACITIVE LOADS The buffers can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a snubber circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain.
Alternatively, the back plate potential can be generated by a DAC and the VCOM amplifier used to buffer the DAC voltage, with gain if necessary. This is shown in Figure 24. In this case, the effective transconductance of the feedback is reduced, thus the amplifier will be more stable, but regulation will be degraded by the feedback factor.
VBOOST FROM DAC + VCOM 1F CERAMIC LOW ESR
R1 R2
FIGURE 24. VCOM USED AS A BUFFER WITH GAIN
CHOICE OF OUTPUT CAPACITOR A 1F ceramic capacitor with low ESR is recommended for this amplifier. (For example, GRM42_ 6X7R105K16). This capacitor determines the stability of the amplifier. Reducing it will make the amplifier less stable, and should be avoided. With a 1F capacitor, the unity gain bandwidth of the amplifier is close to 1MHz when reasonable currents are being drawn. (For lower load currents, the gain and hence bandwidth progressively decreases.) This means the active trans-conductance is:
2 x 1F x 1MHz = 6.28S
The Use of VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back plate of an LCD display. This plate is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rate for the display. Thus the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100mA for typical applications). A simple use of the VCOM amplifier is as a voltage follower, as illustrated in Figure 23. Here, a voltage, corresponding to the mid-DAC potential, is generated by a resistive divider and buffered by the amplifier. The amplifier's stability is designed to be dominated by the load capacitance, thus for very short duration pulses (< 1s) the output capacitor supplies the current. For longer pulses the VCOM amplifier supplies the current. By virtue of its high transconductance which progressively increases as more current is drawn, it can maintain regulation within 5mV as currents up to 100mA are drawn, while consuming only 2mA of quiescent current.
This high transconductance indicates why it is important to have a low ESR capacitor. If:
ESR x 6.28 > 1
then the capacitor will not force the gain to roll off below unity, and subsequent poles can affect stability. The recommended capacitor has an ESR of 10m, but to this must be added the resistance of the board trace between the capacitor and the sense connection - therefore this should be kept short, as illustrated in Figure 21, by the diagonal line to the capacitor. Also ground resistance between the capacitor and the base of R2 must be kept to a minimum. These constraints should be considered when laying out the PCB.
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EL5224, EL5324, EL5424
If the capacitor is increased above 1F, stability is generally improved and short pulses of current will cause a smaller "perturbation" on the VCOM voltage. The speed of response of the amplifier is however degraded as its bandwidth is decreased. At capacitor values around 10F, a subtle interaction with internal DC gain boost circuitry will decrease the phase margin and may give rise to some overshoot in the response. The amplifier will remain stable though. RESPONSE TO HIGH CURRENT SPIKES The VCOM amplifier's output current is limited to 150mA. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen on the s time scale in practical systems and for pulses 2 or 3 times the current limit, the VCOM voltage will have settled again before the next line is processed. when sourcing, and:
P DMAX = i x [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] + [ V SA x I SAA + ( V SA + - V OUTA ) x I LA ]
when sinking. where: * i = 1 to total number of buffers * VS = Total supply voltage of buffer * VSA = Total supply voltage of VCOM * ISMAX = Maximum quiescent current per channel * ISA = Maximum quiescent current of VCOM * VOUTi = Maximum output voltage of the application * VOUTA = Maximum output voltage of VCOM * ILOADi = Load current of buffer * ILA = Load current of VCOM If we set the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves.
Power Dissipation
With the high-output drive capability of the EL5224, EL5324, and EL5424 buffer, it is possible to exceed the 125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- and VSA- pins are connected to ground, two 0.1F ceramic capacitors should be placed from VS+ and VSA+ pins to ground. A 4.7F tantalum capacitor should then be connected from VS+ and VSA+ pins to ground. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Internally, VS+ and VSA+ are shorted together and VS- and VSA- are shorted together. To avoid high current density, the VS+ pin and VSA+ pin must be shorted in the PCB layout. Also, the VS- pin and VSA- pin must be shorted in the PCB layout. Important Note: The metal plane used for heat sinking of the device is electrically connected to the negative supply potential (VS- and VSA-). If VS- and VSA- are tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad must be isolated from any other power planes.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = i x [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] + [ V SA x I SAA + ( V SA + - V OUTA ) x I LA ]
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EL5224, EL5324, EL5424 Package Outline Drawing (HTSSOP)
11
EL5224, EL5324, EL5424 Package Outline Drawing (QFN)
NOTE: The package drawings shown here may not be the latest versions. For the latest revisions, please refer to the Intersil website at www.intersil.com/design/packages/elantec
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12

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